Static random access memory (SRAM) is commonly used in integrated circuits. SRAM cells have the advantageous feature of holding data without requiring refreshing. The SRAM cells include different numbers of transistors, and are often identified by the number of transistors in the SRAM cell. For example, six-transistor (6-T) SRAM cell, eight-transistor (8-T) SRAM cell, and so on. Typically, the transistors in the SRAM cell form a data latch for storing a bit. The SRAM cells are typically arranged as an array having rows and columns. Each row of the SRAM cell array is connected to a word line, which determines whether a current SRAM cell is selected or not. Each column of the SRAM cell array is connected to a bit line (or a pair of bit-lines), which is used for storing a bit into, or reading a bit from, the SRAM cell.
With an increase in down-scaling of the integrated circuits, operating voltages of the integrated circuits, along with the operation voltages of memory circuits are also being reduced. Accordingly, read and write margins of the SRAM cells, which measure how reliably the bits of the SRAM cells can be read from and written into, are also reduced. Due to the existence of static noise, the reduced read and write margins may cause errors in the respective read and write operations.